| Part number | M470L3324BU0-LB3 |
|---|---|
| Product name | DDR SDRAM Unbuffered Module 184pin Unbuffered Module based on 512Mb B-die |
| Manufacturer | SAMSUNG |
| Technical file |
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| EDA/CAD |
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| Product overview | Double-data-rate architecture;two data transfers per clock cycle. DLL aligns DQ and DQS transition with CK transition. Programmable Burst length(2,4,8). Programmable Burst type(sequential and interleave). Edge aligned data output,center aligned data input. Serial presence detect with EEPROM. SSTL_2 Interface |
| Attribute name | Attribute value |
|---|---|
| Creation date | 2005-03-24 |
| Last revised date | 2005-08-05 |
| Class code | XJA653 |
| Product's class name | MEMORY MODULES |
| Family or series name | M470L3324 |
| Product lifecycle stage | Mass production |
| Application scope | Double-data-rate architecture;two data transfers per clock cycle. DLL aligns DQ and DQS transition with CK transition. Programmable Burst length(2,4,8). Programmable Burst type(sequential and interleave). Edge aligned data output,center aligned data input. Serial presence detect with EEPROM. SSTL_2 Interface |
| Package type | 66 TSOP/54 STSOP |
| Mounting method | Surface mount technology |
| Storage temperature[Min] | -55Cel |
| Storage temperature[Max] | 150Cel |
| Memory capacity (bit)[Nom] | 256Mbit |
| Storage size[Nom] | 32Mword |
| Word size[Nom] | 16bit |
| Supply voltage[Min] | 2.3V |
| Supply voltage[Typ] | 2.5V |
| Supply voltage[Max] | 2.7V |
| Cycle time[Max] | 166MHz |
| Access time[Max] | 0.7ns |
| Outline | SO-DIMM |
| Number of connector pins[Nom] | 184 |
| Memory type | DDR SDRAM |
